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tutorials:vec_v1_4:documentation:3_4_wires [2016/05/12 14:27] (current)
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 +~~NOTRANS~~
 +[[..:​start|Index]] - [[3_3_instantiation_of_specifications_without_part_number| Previous ]] - [[3_5_connectors | Next ]] 
 +====== 3.4 Wires ======
 +===== Single Core Specification =====
 +{{map> ​ ..:​diagrams:​3_4_1_single_core_specification.jpg?​656x361 ​ }}
 +  * [[:​models:​vec_v1_1_2:​classes:​wireelement|WireElement @ 276,​115,​377,​141 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​corespecification|CoreSpecification @ 472,​283,​647,​344 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​partversion|PartVersion @ 10,​10,​218,​101 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​insulationspecification|InsulationSpecification @ 213,​276,​435,​352 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wireelementspecification|WireElementSpecification @ 318,​192,​543,​238 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wirespecification|WireSpecification @ 346,​10,​585,​60 ]]
 +{{<map}}
 +<​html> ​  <​head> ​    </​head> ​  <​body> ​    <​p>​ The figure above illustrates the specification of a single core wire. The WireSpecification is the PartOrUsageRelatedSpecification describing the PartVersion. In order to make it possible to reuse the specification of the different WireElements (see Multi Core), the actual definition of the structure of the wire is delegated to a WireElementSpecification. The WireElement defines the context specific identification of a WireElementSpecification in the context of a specific WireSpecification (mainly needed for multi cores, but due to a consistent modeling approach also necessary for single cores). The WireElement is used for reference when a WireSpecification is instantiated (e.g. by a PartOccurrence). ​     </​p> ​   </​body>​ </​html>​ ===== Multi Core Illustration =====
 +{{map> ​ ..:​diagrams:​3_4_2_multi_core_illustration.jpg?​375x245 ​ }}
 +{{<map}}
 +<​html> ​  <​head> ​    </​head> ​  <​body> ​    <​p>​ This is an illustration for the multi core example that describes the specification of a multi core wire. The example uses a multi core, which is insulated with a grey insulation, shielded and which contains two FLRY cores of different colouring that are a twisted pair.      </​p> ​   </​body>​ </​html>​ ===== Multi Core Specification =====
 +{{map> ​ ..:​diagrams:​3_4_3_multi_core_specification.jpg?​895x643 ​ }}
 +  * [[:​models:​vec_v1_1_2:​classes:​wireelement|WireElement @ 24,​24,​135,​82 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wireelement|WireElement @ 549,​10,​660,​68 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wireelement|WireElement @ 185,​122,​333,​180 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​shieldspecification|ShieldSpecification @ 619,​213,​786,​259 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wiregroupspecification|WireGroupSpecification @ 619,​136,​788,​200 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​insulationspecification|InsulationSpecification @ 619,​269,​788,​315 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​corespecification|CoreSpecification @ 290,​514,​465,​575 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​insulationspecification|InsulationSpecification @ 598,​514,​773,​575 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wireelementspecification|WireElementSpecification @ 150,​409,​340,​467 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wirespecification|WireSpecification @ 241,​17,​438,​67 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wireelementspecification|WireElementSpecification @ 514,​416,​725,​474 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​insulationspecification|InsulationSpecification @ 31,​507,​253,​583 ]]
 +  * [[:​models:​vec_v1_1_2:​classes:​wireelementspecification|WireElementSpecification @ 185,​227,​446,​249 ]]
 +{{<map}}
 +<​html> ​  <​head> ​    </​head> ​  <​body> ​    <​p>​ The Figure displays the instantiation of the multi core wire example in the VEC. The hierarchy of the wire is highlighted in the figure in green. The specification of the brown and green FLRY core (0.35-BRGN) is actually the same as the specification in the single core example (highlighted by the red outline in the figure). It is reused and not defined redundantly. Since it is the same WireElementSpecification object, the context specific naming of the WireElement is necessary, as mentioned in single core example (highlighted in yellow). ​    </​p> ​     <p> The only difference between the two WireElements representing the two cores is the coloring of the insulation. Therefore the two WireElementSpecifcations share the same CoreSpecfication,​ but have individual InsulationSpecifications. In the context of the displayed WireSpecification the Brown &amp; Green Core is addressed with the identification “1”, the second Core is addressed with the identification “2”. The two Cores are grouped together by a third WireElementSpecification (2x0.35-BRGN-RTBL). ​    </​p> ​     <p> This third WireElementSpecification defines the type of grouping by a WireGroupSpecification. In the example the Grouping is the definition of a twist of the two Cores. It also defines the insulation around the two SubWireElements by an InsulationSpecification. Since the defined wire has a conductive shield as well, the described WireElementSpecification references a ShieldSpecification,​ too. The cross section area in the ShieldSpecification defines the nominal cross section area of the conductive material used in the shield. ​     </​p> ​   </​body>​ </​html> ​
 +
 +----
 +
 +[[..:​start|Index]] - [[3_3_instantiation_of_specifications_without_part_number| Previous ]] - [[3_5_connectors | Next ]] 
 +~~DISCUSSION~~
  
tutorials/vec_v1_4/documentation/3_4_wires.txt · Last modified: 2016/05/12 14:27 (external edit)