Hierarchical Topologies
Note: There is a newer version of this specification see VEC 2.1.0
Hierarchical topologies are a versatile concept to create harness topologies that have an advanced structural design. For historical reasons, the semantics defined by the VEC for topologies are quite strict and simple, yet sufficient for most cases of traditional wiring harnesses. However, with the advent of modern wiring harness requirements, more advanced concepts are needed for certain applications.
In a regular topology, all wires are routed equally "inside" through a TopologySegment. All wires end at a TopologyNode, there are no connectors or splices positioned within a TopologySegment. All protections, fixings, tapings etc. are placed "around" the wires in a definable order.
With the integration of new technologies (e.g. high voltage, high data rate bus systems) and the improvements of design processes (e.g. integrated 3D design process with traceability and round-trip capabilities) more complex designs must be expressed in a concise, digital evaluable way. Examples for such use cases are:
- Structured harness bundles (e.g. specific wires in a bundle taped together).
- Segments of splices folded into a main bundle in a specific way.
- Reuse of shared parts (e.g. assemblies, right / left back door)
- Refinement of a topology in the design process (e.g. splice positioning after the "geometry design".
To address these requirements, the VEC introduced the concept of hierarchical topologies. In the top left corner of the diagram a simplified illustration shall serve as small example to make the concept more understandable.
A TopologyMappingSpecification is used to associate an "inner" topology with an outer topology. In the illustration the "outer" topology is displayed with grey segments and orange nodes. The two "inner" topologies are displayed with blue & green segments and red nodes.
A NodeMapping is used to define how the nodes of the inner topology relate to the outer topology. An inner node can be either placed exactly on / in an outer node or somewhere within a segment. For the definition of the position of the inner node, the concept of locations is reused.
A SegmentMapping is used to define how the segments of the inner topology relate to the outer topology. An inner segment can run through multiple segments or to stay in a single one. In any case, all outer TopologySegments to which it relates are referenced by a Path.
Some additional restrictions apply on the mapping:
- The representation of the inner / outer relationship with a TopologyMappingSpecification allows the creation of n:m relationships between topologies. However, it is forbidden to create "circular" mappings. If n:m mappings are created, it must be ensured that those mappings shall not exist at same time, or in other words they must be the result of product variance or reuse in different variants.
- "Cross Topology assignment of Components" is forbidden. That means wires are routed strictly in the elements of a single TopologySpecification and other components are placed strictly on a single TopologySpecification.
- If a TopologySpecification is mapped as an inner topology, all its elements shall be mapped.
- A creating system is responsible that the constraints of the topologies are maintained (e.g. that length constraints between inner and outer topologies are satisfied.
Note: This concept was introduced newly with VEC Version 1.2.0. As there are currently no known systems that implement such a concept further detailing of its usage will be done in the Implementation Guidelines accompanying implementations as they occur.